Various fixes to the tree to get coreboot-v2 to build on Solaris

[coreboot.git] / src / mainboard / technexion / tim8690 / Config.lb

diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb
index 9e3ebe7fd4f8ee28c12e6e8779c6a65b88a76230..d18eec931fed78b04b933e646e5f2ca67ff8e4e8 100644 (file)
--- a/src/mainboard/technexion/tim8690/Config.lb
+++ b/src/mainboard/technexion/tim8690/Config.lb
@@ -19,40 +19,7 @@
 ##
 ##
 
-
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
 
 arch i386 end
 
@@ -75,7 +42,7 @@ if HAVE_ACPI_TABLES
        object fadt.o
        makerule dsdt.c
                depends "$(MAINBOARD)/acpi/*.asl"
-               action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+               action  "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
                action  "mv dsdt.hex dsdt.c"
        end
        object ./dsdt.o
@@ -83,34 +50,30 @@ end
 
 #object reset.o
 
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
 
                makerule ./cache_as_ram_auto.o
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
                end
 
        else
 
                makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
                        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
                        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
                end
 
        end
 
-end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end
@@ -118,7 +81,6 @@ if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript      /cpu/amd/car/cache_as_ram.lds
        end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -137,12 +99,10 @@ end
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
        ##
        ## Setup Cache-As-Ram
        ##
        mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -150,12 +110,7 @@ end
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-       if USE_DCACHE_RAM
                ldscript /arch/i386/lib/failover.lds
-       else
-               ldscript /arch/i386/lib/failover.lds
-               mainboardinit ./failover.inc
-       end
 end
 
 ###
@@ -165,16 +120,12 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                initobject cache_as_ram_auto.o
        else
                mainboardinit ./cache_as_ram_auto.inc
        end
 
-end
-
 ##
 ## Include the secondary Configuration files
 ##