* Explicitly add __PRE_RAM__ where it should be added.

[coreboot.git] / src / mainboard / supermicro / x6dhr_ig / auto.c

diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c
index 6df3e66da028321c54b354eacbfe619a773010b1..314cc703250274dca518bd864788c3d6ab48d274 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/auto.c
+++ b/src/mainboard/supermicro/x6dhr_ig/auto.c
@@ -1,17 +1,19 @@
 #define ASSEMBLY 1
+#define __PRE_RAM__
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +22,7 @@
 #include "reset.c"
 #include "x6dhr_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -43,23 +45,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-//void udelay(int usecs)
-//{
-//        int i;
-//        for(i = 0; i < usecs; i++)
-//                outb(i&0xff, 0x80);
-//}
-
-#if 0
-static void hard_reset(void)
-{
-       /* enable cf9 */
-       pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-       /* reset */
-       outb(0x0e, 0x0cf9);
-}
-#endif
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
        /* nothing to do */
@@ -69,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "northbridge/intel/e7520/raminit.c"
+#include "lib/generic_sdram.c"
 
 
 static void main(unsigned long bist)
@@ -102,7 +87,7 @@ static void main(unsigned long bist)
        outb(0x87,0x2e);
        outb(0x87,0x2e);
        pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 
@@ -139,7 +124,7 @@ static void main(unsigned long bist)
 //     dump_ipmi_registers();
        mainboard_set_e7520_leds();     
 //     memreset_setup();
-       sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+       sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 1
        dump_pci_devices();
 #endif