#define ASSEMBLY 1
+#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
-//void udelay(int usecs)
-//{
-// int i;
-// for(i = 0; i < usecs; i++)
-// outb(i&0xff, 0x80);
-//}
-
-#if 0
-static void hard_reset(void)
-{
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-#endif
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
#include "northbridge/intel/e7520/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
// dump_ipmi_registers();
mainboard_set_e7520_leds();
// memreset_setup();
- sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ sdram_initialize(ARRAY_SIZE(mch), mch);
#if 1
dump_pci_devices();
#endif