This does the following:
[coreboot.git] / src / mainboard / supermicro / x6dhe_g2 / devicetree.cb
index 4bb720707c224f68225b24031881801150c96ddf..e621594b937b41806ada5c2bf5969de455a018c5 100644 (file)
@@ -6,7 +6,7 @@ chip northbridge/intel/e7520  # MCH
                device pnp 00.3 off end
        end
        device pci_domain 0 on
-               chip southbridge/intel/i82801er # ICH5R 
+               chip southbridge/intel/i82801ex # ICH5R 
                        register "pirq_a_d" = "0x0b070a05"
                        register "pirq_e_h" = "0x0a808080"