Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / supermicro / h8qme_fam10 / romstage.c

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 5e7b32b4d9162ecd09239ef5e9c00905df11eb44..e77b139745da77209f0d29b18322fc1b983a0eaf 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -22,11 +22,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -35,14 +30,11 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-
 #include <console/console.h>
 #include <lib.h>
-
+#include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -51,19 +43,14 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_SWITCH1 0x70
@@ -78,28 +65,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
-
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -122,10 +97,22 @@ static void sio_setup(void)
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
-#include "spd_addr.h"
+static const u8 spd_addr[] = {
+       //first node
+       RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+       //second node
+       RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+       //third node
+       RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       //forth node
+       RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
 
 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
@@ -310,6 +297,4 @@ post_code(0x40);
 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
-
 }
-