projects / coreboot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Drop excessive whitespace randomly sprinkled in romstage.c files.
[coreboot.git] / src / mainboard / supermicro / h8qme_fam10 / romstage.c
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 3c4dedefaf71b8c905eecd6e6ec2abf8d461a3f3..e77b139745da77209f0d29b18322fc1b983a0eaf 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -19,20 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -41,46 +30,26 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-
-//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
+#include "cpu/amd/model_10xxx/apic_timer.c"
+#include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -96,40 +65,21 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
-#include "resourcemap.c" 
-
+#include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 0 
-#define MCP55_USE_AZA 0
-
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-#include "cpu/amd/car/copy_and_run.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-#include "cpu/amd/model_10xxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
         enable_smbus();
@@ -137,27 +87,37 @@ static void sio_setup(void)
        smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
-#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
+static const u8 spd_addr[] = {
+       //first node
+       RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+       //second node
+       RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+       //third node
+       RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       //forth node
+       RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
 
 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
-void write_GPIO(void)
+static void write_GPIO(void)
 {
        pnp_enter_ext_func_mode(GPIO1_DEV);
        pnp_set_logical_device(GPIO1_DEV);
@@ -217,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 
   post_code(0x30);
- 
+
         if (bist == 0) {
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
@@ -280,7 +240,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
@@ -303,6 +263,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
+       init_timer(); // Need to use TMICT to synconize FID/VID
+
  wants_reset = mcp55_early_setup_x();
 
  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
@@ -326,10 +288,6 @@ post_code(0x3D);
 //printk(BIOS_DEBUG, "enable_smbus()\n");
 //        enable_smbus(); /* enable in sio_setup */
 
-post_code(0x3E);
-
-        memreset_setup();
-
 post_code(0x40);
 
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
@@ -339,6 +297,4 @@ post_code(0x40);
 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
-
 }
-
my coreboot WIP stuff (asus m5a99x-evo board)