* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RAMINIT_SYSINFO 1
-
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
-
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 0
-#define MCP55_USE_AZA 0
-
-#define MCP55_PCI_E_X_0 4
-
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
-#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
}
-#include "spd_addr.h"
+static const u8 spd_addr[] = {
+ //first node
+ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+ //third node
+ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ //forth node
+ RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
- mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
- pnp_enter_ext_func_mode(SERIAL_DEV);
- pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
+ w83627hf_set_clksel_48(DUMMY_DEV);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- uart_init();
console_init();
write_GPIO();
printk(BIOS_DEBUG, "\n");
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
raminit_amdmct(sysinfo);
post_code(0x41);
-// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
-
}
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ * This routine is called every time a non-coherent chain is processed.
+ * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ * swap list. The first part of the list controls the BUID assignment and the
+ * second part of the list provides the device to device linking. Device orientation
+ * can be detected automatically, or explicitly. See documentation for more details.
+ *
+ * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ * based on each device's unit count.
+ *
+ * Parameters:
+ * @param[in] u8 node = The node on which this chain is located
+ * @param[in] u8 link = The link on the host for this chain
+ * @param[out] u8** list = supply a pointer to a list
+ * @param[out] BOOL result = true to use a manual list
+ * false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ /* If the BUID was adjusted in early_ht we need to do the manual override */
+ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+ printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+ if ((node == 0) && (link == 0)) { /* BSP SB link */
+ *List = swaplist;
+ return 1;
+ }
+ }
+
+ return 0;
+}
projects / coreboot.git / blobdiff