outb(value, 0x80);
}
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
- /* nothing to do */
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITCH2 0x72
+ smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
+ smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
}
static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_10xxx/fidvid.c"
-#endif
-
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
}
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- unsigned last_boot_normal_x = last_boot_normal();
-
- /* Is this a cpu only reset? or Is this a secondary cpu? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_x) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
-
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
-
- sio_setup();
-
- /* Setup the mcp55 */
- mcp55_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal_x) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- __asm__ volatile ("jmp __fallback_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- )
-#endif
- ;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- #if CONFIG_USE_FAILOVER_IMAGE==1
- failover_process(bist, cpu_init_detectedx);
- #else
- real_main(bist, cpu_init_detectedx);
- #endif
-#else
- #if CONFIG_USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
- #endif
- real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
+#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
+#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+void write_GPIO(void)
+{
+ pnp_enter_ext_func_mode(GPIO1_DEV);
+ pnp_set_logical_device(GPIO1_DEV);
+ pnp_write_config(GPIO1_DEV, 0x30, 0x01);
+ pnp_write_config(GPIO1_DEV, 0x60, 0x00);
+ pnp_write_config(GPIO1_DEV, 0x61, 0x00);
+ pnp_write_config(GPIO1_DEV, 0x62, 0x00);
+ pnp_write_config(GPIO1_DEV, 0x63, 0x00);
+ pnp_write_config(GPIO1_DEV, 0x70, 0x00);
+ pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
+ pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
+ pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
+ pnp_exit_ext_func_mode(GPIO1_DEV);
+
+ pnp_enter_ext_func_mode(GPIO2_DEV);
+ pnp_set_logical_device(GPIO2_DEV);
+ pnp_write_config(GPIO2_DEV, 0x30, 0x01);
+ pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
+ pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
+ pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
+ pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
+ pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
+ pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
+ pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
+ pnp_exit_ext_func_mode(GPIO2_DEV);
+
+ pnp_enter_ext_func_mode(GPIO3_DEV);
+ pnp_set_logical_device(GPIO3_DEV);
+ pnp_write_config(GPIO3_DEV, 0x30, 0x00);
+ pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
+ pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
+ pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
+ pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
+ pnp_exit_ext_func_mode(GPIO3_DEV);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 wants_reset;
msr_t msr;
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+
+ set_bsp_node_CHtExtNodeCfgEn();
+ enumerate_ht_chain();
+
+ sio_setup();
+
+ /* Setup the mcp55 */
+ mcp55_enable_rom();
+ }
+
post_code(0x30);
if (bist == 0) {
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
- uart_init();
- console_init();
- printk_debug("\n");
-
+ uart_init();
+ console_init();
+ write_GPIO();
+ printk(BIOS_DEBUG, "\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
val = cpuid_eax(1);
- printk_debug("BSP Family_Model: %08x \n", val);
- printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
- printk_debug("bsp_apicid = %02x \n", bsp_apicid);
- printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+ printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
- printk_debug("start_other_cores()\n");
+ printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#if FAM10_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
- printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
wants_reset = mcp55_early_setup_x();
}
if (wants_reset)
- printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+ printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
-printk_debug("fill_mem_ctrl()\n");
+printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x3D);
-//printk_debug("enable_smbus()\n");
+//printk(BIOS_DEBUG, "enable_smbus()\n");
// enable_smbus(); /* enable in sio_setup */
post_code(0x3E);
post_code(0x40);
- printk_debug("raminit_amdmct()\n");
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
-// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
}
-
-#endif
projects / coreboot.git / blobdiff