* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
#define RAMINIT_SYSINFO 1
#define FAM10_SCAN_PCI_BUS 0
#define SET_NB_CFG_54 1
#endif
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-static void post_code(u8 value) {
- outb(value, 0x80);
-}
-
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-
static void sio_setup(void)
{
-
- unsigned value;
uint32_t dword;
uint8_t byte;
enable_smbus();
}
#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
-void write_GPIO(void)
+static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
pnp_set_logical_device(GPIO1_DEV);
post_code(0x38);
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
//printk(BIOS_DEBUG, "enable_smbus()\n");
// enable_smbus(); /* enable in sio_setup */
-post_code(0x3E);
-
- memreset_setup();
-
post_code(0x40);
-
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);