Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / supermicro / h8dmr_fam10 / Kconfig
index 67ec6824fda4db2ecc07a3cefa20116f0e9bfc80..4b31bf30a7c75b372b1aa3c5afad50219f68713e 100644 (file)
-config BOARD_SUPERMICRO_H8DMR_FAM10
-       bool "H8DMR_FAM10 (Fam10)"
+if BOARD_SUPERMICRO_H8DMR_FAM10
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
-       select CPU_AMD_FAM10
        select CPU_AMD_SOCKET_F_1207
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDFAM10
-       select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
+       select MCP55_USE_AZA
        select SUPERIO_WINBOND_W83627HF
+       select HAVE_BUS_CONFIG
+       select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_PRINTK_IN_CAR
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
-       select IOAPIC
+       select LIFT_BSP_APIC_ID
        select AMDMCT
+       select BOARD_ROMSIZE_KB_1024
+       select RAMINIT_SYSINFO
+       select TINY_BOOTBLOCK
+       select ENABLE_APIC_EXT_ID
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
        default supermicro/h8dmr_fam10
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config DCACHE_RAM_BASE
        hex
-       default 0xc8000
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0xc4000
 
 config DCACHE_RAM_SIZE
        hex
-       default 0x08000
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0x0c000
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
-       default 0x01000
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0x04000
 
-config APIC_ID_OFFSET
+config RAMBASE
        hex
-       default 0x10
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0x200000
 
-config SB_HT_CHAIN_ON_BUS0
-       int
-       default 2
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+config RAMTOP
+       hex
+       default 0x1000000
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-       bool
-       default n
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+config HEAP_SIZE
+       hex
+       default 0xc0000
 
-config LB_CKS_RANGE_END
+config APIC_ID_OFFSET
+       hex
+       default 0x0
+
+config MEM_TRAIN_SEQ
        int
-       default 122
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 2
 
-config LB_CKS_LOC
+config SB_HT_CHAIN_ON_BUS0
        int
-       default 123
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 2
 
 config MAINBOARD_PART_NUMBER
        string
-       default "H8DMR_FAM10 FAM10"
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
-
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default "H8DMR-i2 (Fam10)"
 
 config MAX_CPUS
        int
-       default 4
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 8
 
 config MAX_PHYSICAL_CPUS
        int
        default 2
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config HT_CHAIN_END_UNITID_BASE
        hex
-       default 0x0
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0x20
 
 config HT_CHAIN_UNITID_BASE
        hex
-       default 0x0
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
-
-config USE_INIT
-       bool
-       default n
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+       default 0x1
 
 config SB_HT_CHAIN_ON_BUS0
        int
        default 2
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config IRQ_SLOT_COUNT
        int
        default 11
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config AMD_UCODE_PATCH_FILE
        string
        default "mc_patch_0100009f.h"
-       depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SERIAL_CPU_INIT
+       bool
+       default n
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+       hex
+       default 0x1511
+
+endif # BOARD_SUPERMICRO_H8DMR_FAM10