Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / supermicro / h8dmr / resourcemap.c

diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c
index 0a26d002602563541858132a6c8f4f1cf12a9f4d..db5d5fe185e11fad3e32008d11e254baabc6a03c 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr/resourcemap.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
                 *         1 = base/limit registers i are read-only
                 * [ 7: 4] Reserved
                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-                *         This field defines the upper address bits of a 40bit address 
+                *         This field defines the upper address bits of a 40bit address
                 *         that defines the start of memory-mapped I/O region i
                 */
                PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -217,7 +217,7 @@ static void setup_mb_resource_map(void)
                 * [ 3: 2] Reserved
                 * [ 4: 4] VGA Enable
                 *         0 = VGA matches Disabled
-                *         1 = matches all address < 64K and where A[9:0] is in the 
+                *         1 = matches all address < 64K and where A[9:0] is in the
                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
                 * [ 5: 5] ISA Enable
                 *         0 = ISA matches Disabled
@@ -225,7 +225,7 @@ static void setup_mb_resource_map(void)
                 *             from matching agains this base/limit pair
                 * [11: 6] Reserved
                 * [24:12] PCI I/O Base i
-                *         This field defines the start of PCI I/O region n 
+                *         This field defines the start of PCI I/O region n
                 * [31:25] Reserved
                 */
                PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,14 +270,14 @@ static void setup_mb_resource_map(void)
                 *         This field defines the highest bus number in configuration region i
                 */
                PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
-               PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+               PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
                PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-               PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+               PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
        };
 
        int max;
-       max = sizeof(register_values)/sizeof(register_values[0]);
+       max = ARRAY_SIZE(register_values);
        setup_resource_map(register_values, max);
 }