Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / supermicro / h8dme / romstage.c

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 5b158e0f56fd8b6c51db8d5166f797c89c7f19e0..de3bc2c35f8d704222731d922fe4182e21bc7414 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -16,21 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
-#define K8_ALLOCATE_IO_RANGE 1
-
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-// used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -43,43 +28,26 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-
-// #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -154,35 +122,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
-
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -220,15 +170,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  */
        static const uint16_t spd_addr[] = {
                // Node 0
-               RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
-                   RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
-               RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
-                   RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
+               RC0 | DIMM0, RC0 | DIMM2,
+               RC0 | DIMM4, RC0 | DIMM6,
+               RC0 | DIMM1, RC0 | DIMM3,
+               RC0 | DIMM5, RC0 | DIMM7,
                // Node 1
-               RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
-                   RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
-               RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
-                   RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
+               RC1 | DIMM0, RC1 | DIMM2,
+               RC1 | DIMM4, RC1 | DIMM6,
+               RC1 | DIMM1, RC1 | DIMM3,
+               RC1 | DIMM5, RC1 | DIMM7,
        };
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
@@ -292,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
        ht_setup_chains_x(sysinfo);     // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
        {
                msr_t msr;
@@ -322,7 +272,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        }
 #endif
 
-#if 1
+       init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
        needs_reset |= optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        needs_reset |= mcp55_early_setup_x();
@@ -332,7 +283,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                print_info("ht reset -\n");
                soft_reset();
        }
-#endif
+
        allow_all_aps_stop(bsp_apicid);
 
        //It's the time to set ctrl in sysinfo now;
@@ -340,15 +291,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        enable_smbus();         /* enable in sio_setup */
 
-       memreset_setup();
-
-       //do we need apci timer, tsc...., only debug need it for better output
        /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
 
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
        post_cache_as_ram();    // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-