-#define K8_ALLOCATE_IO_RANGE 1
-
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
-
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
{
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
static const uint16_t spd_addr [] = {
// Node 0
- (0xa<<3)|0, (0xa<<3)|2, 0, 0,
- (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// Node 1
- (0xa<<3)|4, (0xa<<3)|6, 0, 0,
- (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
int needs_reset;
enumerate_ht_chain();
sio_setup();
-
- /* Setup the ck804 */
- ck804_enable_rom();
}
if (bist == 0) {
post_cache_as_ram();
}
-