Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / sunw / ultra40 / irq_tables.c

diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c
index c5a905936689f91cfa817c71db23b479461f972b..324c87d9950dfc6caf028a625a68d1176febefc4 100644 (file)
--- a/src/mainboard/sunw/ultra40/irq_tables.c
+++ b/src/mainboard/sunw/ultra40/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -9,12 +9,13 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
                uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
                uint8_t slot, uint8_t rfu)
 {
-        pirq_info->bus = bus; 
+        pirq_info->bus = bus;
         pirq_info->devfn = devfn;
                 pirq_info->irq[0].link = link0;
                 pirq_info->irq[0].bitmap = bitmap0;
@@ -51,7 +52,7 @@ extern  unsigned hcdn[];
 extern  unsigned sbdn3;
 extern  unsigned sbdnb;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
@@ -71,19 +72,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
        pirq = (void *)(addr);
        v = (uint8_t *)(addr);
-       
+
        pirq->signature = PIRQ_SIGNATURE;
        pirq->version  = PIRQ_VERSION;
-       
+
        pirq->rtr_bus = bus_ck804_0;
        pirq->rtr_devfn = ((sbdn+9)<<3)|0;
 
        pirq->exclusive_irqs = 0;
-       
+
        pirq->rtr_vendor = 0x10de;
        pirq->rtr_device = 0x005c;
 
@@ -99,9 +100,9 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //pcix bridge
         write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
         pirq_info++; slot_num++;
-        
-       if(pci1234[2] & 0xf) {     
-       //second pci beidge   
+
+       if(pci1234[2] & 0xf) {
+       //second pci beidge
                write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
                pirq_info++; slot_num++;
        }
@@ -138,10 +139,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //Slot2 pci
         write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
         pirq_info++; slot_num++;
-//nic   
+//nic
         write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
         pirq_info++; slot_num++;
-//Slot3 PCIE x16 
+//Slot3 PCIE x16
         write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
         pirq_info++; slot_num++;
 
@@ -161,11 +162,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
         write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
         pirq_info++; slot_num++;
 #endif
-                
-       pirq->size = 32 + 16 * slot_num; 
+
+       pirq->size = 32 + 16 * slot_num;
 
         for (i = 0; i < pirq->size; i++)
-                sum += v[i];   
+                sum += v[i];
 
        sum = pirq->checksum - sum;