Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / roda / rk886ex / romstage.c

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 044107cd5aa4326d55d0d9fbff95fd1c4fe22b5b..aef61671dabdf1f8bbdef1d86cfd7c8c3c6c3614 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -21,12 +21,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-// Rocky freezing temperature settings:
-#define MAXIMUM_SUPPORTED_FREQUENCY 400
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
@@ -34,28 +28,18 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -71,18 +55,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010030, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ
@@ -282,15 +254,20 @@ void main(unsigned long bist)
                enable_lapic();
        }
 
+       /* Force PCIRST# */
+       pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+       udelay(200 * 1000);
+       pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+
        ich7_enable_lpc();
        early_superio_config();
 
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       i82801gx_enable_usbdebug(1);
+       early_usbdebug_init();
 #endif
 
        console_init();
@@ -299,8 +276,9 @@ void main(unsigned long bist)
        report_bist_failure(bist);
 
        if (MCHBAR16(SSKPD) == 0xCAFE) {
-               printk(BIOS_DEBUG, "soft reset detected.\n");
-               boot_mode = 1;
+               printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+               outb(0x6, 0xcf9);
+               while (1) asm("hlt");
        }
 
        /* Perform some early chipset initialization required
@@ -353,7 +331,7 @@ void main(unsigned long bist)
 
 #if !CONFIG_HAVE_ACPI_RESUME
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
        sdram_dump_mchbar_registers();
 
        {
@@ -393,4 +371,3 @@ void main(unsigned long bist)
        }
 #endif
 }
-