i82801gx: replace cafed00d/cafebabe by defines

[coreboot.git] / src / mainboard / roda / rk886ex / romstage.c

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 803aaee89b5751ee4f40499bc3842720ed2d3b40..2af7c2beb5859d2598dc06e29f872c368a04e113 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -21,12 +21,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-// Rocky freezing temperature settings:
-#define MAXIMUM_SUPPORTED_FREQUENCY 400
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
@@ -34,61 +28,57 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-
-#include "northbridge/intel/i945/udelay.c"
-
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+#include "option_table.h"
+
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
        outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
        outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
-       outl(0x7dc07f83, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
+       // ------------------------------------------------------------
+       // 0 - GPO6  - Enable power of SATA channel 0
+       // 0 - GPO9  - Wireless LAN power on
+       // 0 - GPO15 - FAN on
+       // 1 - GPO22 - FWH WP
+       // 1 - GPO24 - GPS on
+       // 0 - GPO25 - External Antenna Mux on
+       // 0 - GPO26 - BT on
+       // 0 - GPO27 - GSM on
+       outl(0x01400000, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
+       // ------------------------------------------------------------
        /* Output Control Registers */
        outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
        /* Input Control Registers */
        outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
        outl(0x000100e8, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
        outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
-       outl(0x00010030, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
-}
-
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
+       // ------------------------------------------------------------
+       // 1 - GPO48 - FWH TBL#
+       outl(0x00010000, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
+       // ------------------------------------------------------------
 }
 
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
+       int lpt_en = 0;
+       if (read_option(lpt, 0) != 0) {
+              lpt_en = 1<<2; // enable LPT
+       }
        // Enable Serial IRQ
        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
        // decode range
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
        // decode range
-       pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+       pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
        // Enable 0x02e0
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
@@ -263,38 +253,23 @@ static void init_artec_dongle(void)
 
 #include <cbmem.h>
 
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM__ being set during CAR stage (in order to compile the
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
 void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
-
-       ich7_enable_lpc();
 
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+       udelay(200 * 1000);
+       pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
 
+       ich7_enable_lpc();
        early_superio_config();
 
        /* Set up the console */
-       uart_init();
-
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -338,7 +313,7 @@ void main(unsigned long bist)
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, NULL);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
@@ -356,7 +331,7 @@ void main(unsigned long bist)
 
 #if !CONFIG_HAVE_ACPI_RESUME
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
        sdram_dump_mchbar_registers();
 
        {
@@ -392,8 +367,7 @@ void main(unsigned long bist)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
-               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
        }
 #endif
 }
-