/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
#include <string.h>
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/pci_ids.h>
#include "dmi.h"
-extern unsigned char AmlCode[];
+extern const unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
-
-#define OLD_ACPI 0
-#if OLD_ACPI
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- memset (gnvs, 0, sizeof(global_nvs_t));
-
- gnvs->LIDS = 1;
- gnvs->PWRS = 1;
-
- gnvs->ACTT = 0x37;
- gnvs->PSVT = 0x4f;
-
- gnvs->TC1V = 0x00;
- gnvs->TC2V = 0x0a;
- gnvs->TSPV = 0x02;
-
- gnvs->CRTT = 0x77;
-
- gnvs->B0SC = 0x54;
- gnvs->APIC = 0x01;
- gnvs->MPEN = 0x01;
-
- gnvs->PPCM = 0x02;
- gnvs->PCP0 = 0xbf;
- gnvs->PCP1 = 0xbf;
-
- gnvs->CMAP = 0x01;
- gnvs->CMBP = 0x01;
- gnvs->LT0 = 0x01;
- gnvs->FDCP = 0x01;
- gnvs->CMCP = 0x01;
- gnvs->CMDP = 0x01;
- gnvs->P2M = 0x02;
-
- gnvs->IGDS = 0x01;
-
- gnvs->CADL = 0x09;
- gnvs->PADL = 0x09;
-
- gnvs->NDID = 3;
- gnvs->DID1 = 0x80000100;
- gnvs->DID2 = 0x80000240;
- gnvs->DID3 = 0x80000410;
- gnvs->DID4 = 0x80000410;
- gnvs->DID5 = 0x00000005;
-
- gnvs->ALAF = 0x64;
- gnvs->LLOW = 0x2c;
- gnvs->LHIH = 0x01;
-
- // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
- // oemb->topm = tolud;
-}
-#endif
-#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->did[4] = 0x00000005;
}
-void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-
-
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
MP_IRQ_POLARITY_HIGH |
MP_IRQ_TRIGGER_EDGE, 0x01);
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 1, MP_IRQ_POLARITY_HIGH |
+ current, 1, MP_IRQ_POLARITY_HIGH |
MP_IRQ_TRIGGER_EDGE, 0x01);
/* INT_SRC_OVR */
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
- printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
/*
* We explicitly add these tables later on:
*/
- printk_debug("ACPI: * HPET\n");
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
- printk_debug("ACPI: * MADT\n");
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
ALIGN_CURRENT;
acpi_add_table(rsdp, madt);
- printk_debug("ACPI: * MCFG\n");
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
- printk_debug("ACPI: * FACS\n");
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
acpi_create_facs(facs);
dsdt = (acpi_header_t *) current;
- current += ((acpi_header_t *) AmlCode)->length;
- memcpy((void *) dsdt, (void *) AmlCode,
- ((acpi_header_t *) AmlCode)->length);
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
- /* Fix up global NVS region for SMI handler. The GNVS region lives
+ /* Fix up global NVS region for SMI handler. The GNVS region lives
* in the (high) table area. The low memory map looks like this:
*
* 0x00000000 - 0x000003ff Real Mode IVT
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
- printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
break;
}
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC
- printk_debug("ACPI: * SLIC\n");
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
ALIGN_CURRENT;
acpi_add_table(rsdp, slic);
#endif
- printk_debug("ACPI: * FADT\n");
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
ALIGN_CURRENT;
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
- printk_debug("ACPI: * SSDT\n");
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "COREBOOT");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
ALIGN_CURRENT;
- printk_debug("current = %lx\n", current);
+ printk(BIOS_DEBUG, "current = %lx\n", current);
- printk_debug("ACPI: * DMI (Linux workaround)\n");
+ printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n");
memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
#if CONFIG_WRITE_HIGH_TABLES == 1
memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
ALIGN_CURRENT;
#endif
- printk_info("ACPI: done.\n");
+ printk(BIOS_INFO, "ACPI: done.\n");
/* Enable Dummy DCC ON# for DVI */
- printk_debug("Laptop handling...\n");
+ printk(BIOS_DEBUG, "Laptop handling...\n");
outb(inb(0x60f) & ~(1 << 5), 0x60f);
return current;
projects / coreboot.git / blobdiff