Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / rca / rm4100 / romstage.c

diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 908722a55f1dab10a6e564e5cbed0a4048627102..c974ebeeddddf2643773bd538c7c4689b12b32b2 100644 (file)
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
@@ -36,24 +36,24 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
  * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
+ * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
+ * (0x51/DIMM1).
  */
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        int i;
 
-       if (device == 0x50) {
+       if (device == DIMM0) {
                return smbus_read_byte(device, address);
-       } else if (device == 0x51) {
+       } else if (device == DIMM1) {
                for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
                        if (spd_table[i].address == address)
                                return spd_table[i].data;
@@ -127,4 +127,3 @@ void main(unsigned long bist)
        /* ram_check(0, 640 * 1024); */
        /* ram_check(64512 * 1024, 65536 * 1024); */
 }
-