AMD Geode cpus: apply un-written naming rules

[coreboot.git] / src / mainboard / pcengines / alix2d / romstage.c

diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 44e14ac7ec23954fe9c38472978d422f672fb2df..0e8cc63a1658dedc1a3cde3ec651b148e3de6c42 100644 (file)
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -30,18 +30,14 @@
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.
  *
@@ -88,7 +84,7 @@ static u8 spd_read_byte(u8 device, u8 address)
        print_debug("spd_read_byte dev ");
        print_debug_hex8(device);
 
-       if (device != (0x50 << 1)) {
+       if (device != DIMM0) {
                print_debug(" returns 0xff\n");
                return 0xff;
        }
@@ -110,9 +106,9 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 /** Early mainboard specific GPIO setup. */
 static void mb_gpio_init(void)
@@ -129,26 +125,22 @@ static void mb_gpio_init(void)
         *       Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
         *         This resets the GPIO I/O space to 0x6100.
         *         This may break other things, though.
-     */
+        */
        outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
        outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
        outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
 
        /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */  /* Led 1 enabled  */
-    outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);        /* Led 2 disabled */
+       outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);        /* Led 2 disabled */
        outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);       /* Led 3 disabled */
-
-
 }
 
 void main(unsigned long bist)
 {
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {0x50}},
+               {.channel0 = {DIMM0}},
        };
 
-       post_code(0x01);
-
        SystemPreInit();
        msr_init();
 
@@ -159,7 +151,6 @@ void main(unsigned long bist)
         */
        cs5536_setup_onchipuart(1);
        mb_gpio_init();
-       uart_init();
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -171,10 +162,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory */
-       /* Enable this only if you are having questions. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Switch from Cache as RAM to real RAM.
         *
         * There are two ways we could think about this.
@@ -208,4 +195,3 @@ void main(unsigned long bist)
        void done_cache_as_ram_main(void);
        done_cache_as_ram_main();
 }
-