Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / pcengines / alix1c / romstage.c

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index c4a9cc98e53f810613e78d3582bf3d970e2d07cb..209485ec64085e4f719c219276133594420c6e40 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -18,15 +18,15 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <spd.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
@@ -36,9 +36,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
-void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
 
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -88,7 +86,7 @@ static u8 spd_read_byte(u8 device, u8 address)
        print_debug("spd_read_byte dev ");
        print_debug_hex8(device);
 
-       if (device != (0x50 << 1)) {
+       if (device != DIMM0) {
                print_debug(" returns 0xff\n");
                return 0xff;
        }
@@ -106,43 +104,18 @@ static u8 spd_read_byte(u8 device, u8 address)
 #define PLLMSRhi       0x00001490      /* Manual settings for the PLL */
 #define PLLMSRlo       0x02000030
 
-#define DIMM0          0xa0
-#define DIMM1          0xa2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
 
-static void msr_init(void)
-{
-       msr_t msr;
-
-       /* Setup access to the MC for under 1MB. Note MC not setup yet. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x10010000;
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff00;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff00;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-}
-
-/** Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-}
-
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {0x50}},
+               {.channel0 = {DIMM0}},
        };
 
        post_code(0x01);
@@ -157,13 +130,15 @@ void cache_as_ram_main(void)
         */
        cs5536_disable_internal_uart();
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       mb_gpio_init();
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
@@ -204,4 +179,3 @@ void cache_as_ram_main(void)
        void done_cache_as_ram_main(void);
        done_cache_as_ram_main();
 }
-