Let Geode GX2 use geode_post_code.h just like Geode LX

[coreboot.git] / src / mainboard / olpc / rev_a / romstage.c

diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c
index 12ff739a4e896ee74ac52b47d7ebfd461467ce82..7f8779f72011db8028f7147607130c3073eb71db 100644 (file)
--- a/src/mainboard/olpc/rev_a/romstage.c
+++ b/src/mainboard/olpc/rev_a/romstage.c
@@ -1,19 +1,15 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
+#include <cpu/amd/geode_post_code.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -38,9 +34,6 @@ static inline unsigned int fls(unsigned int x)
         return r;
 }
 
-
-
-
 /* sdram parameters for OLPC:
        row address = 13
        col address = 9
@@ -56,7 +49,7 @@ static inline unsigned int fls(unsigned int x)
        Trrd=2 (act2act)
        Tref=17.8ms
   */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
        /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
         *                      component Banks (byte 17) * module banks, side (byte 5) *
@@ -96,7 +89,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 
        print_debug("computed msr.hi ");
        print_debug_hex32(msr.hi);
-       print_debug("\r\n");
+       print_debug("\n");
 
        /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
        /* well, it may be close. It's about 200,000 ticks */
@@ -106,11 +99,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
        /* timing and mode ... */
 
        msr = rdmsr(0x20000019);
-       
-       /* per standard bios settings */        
+
+       /* per standard bios settings */
 
        msr.hi = 0x18000108;
-       msr.lo = 
+       msr.lo =
                        (6<<28) |               // cas_lat
                        (10<<24)|               // ref2act
                        (7<<20)|                // act2pre
@@ -120,8 +113,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
                        (2<<6)|                 // dplwr
                        (2<<4)|                 // dplrd
                        (3);                    // dal
-       /* the msr value reported by quanta is very, very different. 
-        * we will go with that value for now. 
+       /* the msr value reported by quanta is very, very different.
+        * we will go with that value for now.
         */
        msr.lo = 0x286332a3;
 
@@ -139,16 +132,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
-       __builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
-
-       __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
-        __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void gpio_init(void)
 {
@@ -162,7 +146,7 @@ static void gpio_init(void)
        outl(m, GPIOL_EVENTS_ENABLE);
 }
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
        static const struct mem_controller memctrl [] = {
                {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -182,13 +166,17 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset();
 
        cpuRegInit();
        print_err("done cpuRegInit\n");
-       
+
        sdram_initialize(1, memctrl);
-       
+
        /* Check all of memory */
        //ram_check(0x00000000, 640*1024);
 }
+