Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / nvidia / l1_2pvv / Kconfig

diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 09a3d68553d7391c5bed7e15b5b54e9941ee19f2..ab361f175f0aa06d5f2caeb2e840d2c27c0370aa 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -1,23 +1,21 @@
 config BOARD_NVIDIA_L1_2PVV
-       bool "L1 2PVV"
+       bool "l1_2pvv"
        select ARCH_X86
-       select CPU_AMD_K8
        select CPU_AMD_SOCKET_F
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
        select SUPERIO_WINBOND_W83627EHG
+       select HAVE_BUS_CONFIG
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
        select USE_PRINTK_IN_CAR
        select USE_DCACHE_RAM
        select HAVE_HARD_RESET
-       select IOAPIC
-       select MEM_TRAIN_SEQ
-       select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+       select LIFT_BSP_APIC_ID
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
- 
+
 config MAINBOARD_DIR
        string
        default nvidia/l1_2pvv
@@ -27,7 +25,7 @@ config DCACHE_RAM_BASE
        hex
        default 0xc8000
        depends on BOARD_NVIDIA_L1_2PVV
-       
+
 config DCACHE_RAM_SIZE
        hex
        default 0x08000
@@ -39,28 +37,18 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
        depends on BOARD_NVIDIA_L1_2PVV
 
 config APIC_ID_OFFSET
-       hex     
-       default 16
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config SB_HT_CHAIN_ON_BUS0
-       int
-       default 2
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config LB_CKS_RANGE_START
-       int
-       default 49
+       hex
+       default 0x10
        depends on BOARD_NVIDIA_L1_2PVV
 
-config LB_CKS_RANGE_END
+config MEM_TRAIN_SEQ
        int
-       default 122
+       default 1
        depends on BOARD_NVIDIA_L1_2PVV
 
-config LB_CKS_LOC
+config SB_HT_CHAIN_ON_BUS0
        int
-        default 123
+       default 2
        depends on BOARD_NVIDIA_L1_2PVV
 
 config MAINBOARD_PART_NUMBER
@@ -73,16 +61,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_NVIDIA_L1_2PVV
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000
@@ -90,21 +68,16 @@ config HW_MEM_HOLE_SIZEK
 
 config MAX_CPUS
        int
-       default 2
+       default 4
        depends on BOARD_NVIDIA_L1_2PVV
 
 config MAX_PHYSICAL_CPUS
        int
-       default 1
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config AP_CODE_IN_CAR
-       bool    
-       default n
+       default 2
        depends on BOARD_NVIDIA_L1_2PVV
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool    
+       bool
        default n
        depends on BOARD_NVIDIA_L1_2PVV
 
@@ -114,22 +87,12 @@ config HT_CHAIN_UNITID_BASE
        depends on BOARD_NVIDIA_L1_2PVV
 
 config HT_CHAIN_END_UNITID_BASE
-       hex     
-       default 0x0
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config USE_INIT
-       bool
-       default n
+       hex
+       default 0x20
        depends on BOARD_NVIDIA_L1_2PVV
 
 config SERIAL_CPU_INIT
-       bool    
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config WAIT_BEFORE_CPUS_INIT
-       bool    
+       bool
        default n
        depends on BOARD_NVIDIA_L1_2PVV