Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / nvidia / l1_2pvv / Kconfig

diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index d948c228aec521db182f87f522231c435447d526..80f5e3458bde8bfc6a9d2541f1e22d3741b9654b 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -4,19 +4,25 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
+       select MCP55_USE_AZA
        select SUPERIO_WINBOND_W83627EHG
        select HAVE_OPTION_TABLE
        select HAVE_BUS_CONFIG
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select CACHE_AS_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
        string
@@ -42,6 +48,10 @@ config MEM_TRAIN_SEQ
        int
        default 1
 
+config MCP55_NUM
+       int
+       default 2
+
 config SB_HT_CHAIN_ON_BUS0
        int
        default 2
@@ -54,10 +64,6 @@ config PCI_64BIT_PREF_MEM
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 4
@@ -66,10 +72,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 2
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x0
@@ -94,4 +96,8 @@ config IRQ_SLOT_COUNT
        int
        default 11
 
+config MCP55_PCI_E_X_0
+       int
+       default 2
+
 endif # BOARD_NVIDIA_L1_2PVV