Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / nvidia / l1_2pvv / Kconfig

diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 5794521b3a163702f7331bd3626e8cbe1aac505f..80f5e3458bde8bfc6a9d2541f1e22d3741b9654b 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -1,113 +1,103 @@
-config BOARD_NVIDIA_L1_2PVV
-       bool "l1_2pvv"
+if BOARD_NVIDIA_L1_2PVV
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
+       select MCP55_USE_AZA
        select SUPERIO_WINBOND_W83627EHG
        select HAVE_OPTION_TABLE
        select HAVE_BUS_CONFIG
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_PRINTK_IN_CAR
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
        string
        default nvidia/l1_2pvv
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config DCACHE_RAM_BASE
        hex
        default 0xc8000
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config DCACHE_RAM_SIZE
        hex
        default 0x08000
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
        default 0x01000
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config APIC_ID_OFFSET
        hex
        default 0x10
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config MEM_TRAIN_SEQ
        int
        default 1
-       depends on BOARD_NVIDIA_L1_2PVV
+
+config MCP55_NUM
+       int
+       default 2
 
 config SB_HT_CHAIN_ON_BUS0
        int
        default 2
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config MAINBOARD_PART_NUMBER
        string
        default "l1_2pvv"
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config PCI_64BIT_PREF_MEM
        bool
-        default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-       depends on BOARD_NVIDIA_L1_2PVV
+       default n
 
 config MAX_CPUS
        int
        default 4
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config MAX_PHYSICAL_CPUS
        int
        default 2
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x0
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config HT_CHAIN_END_UNITID_BASE
        hex
        default 0x20
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config SERIAL_CPU_INIT
        bool
        default n
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
        hex
        default 0x1022
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
        hex
        default 0x2b80
-       depends on BOARD_NVIDIA_L1_2PVV
 
 config IRQ_SLOT_COUNT
        int
        default 11
-       depends on BOARD_NVIDIA_L1_2PVV
+
+config MCP55_PCI_E_X_0
+       int
+       default 2
+
+endif # BOARD_NVIDIA_L1_2PVV