##
chip northbridge/intel/i440bx # Northbridge
- device apic_cluster 0 on # APIC cluster
- chip cpu/intel/socket_PGA370 # CPU
- device apic 0 on end # APIC
+ device lapic_cluster 0 on # (L)APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU socket
+ device lapic 0 on end # Local APIC of the CPU
end
end
device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
+ device pci f.0 on
+ chip southbridge/ti/pci1x2x
+ device pci 00.0 on
+
+ end
+ register "cltr" = "0x40"
+ register "bcr" = "0x7c0"
+ register "scr" = "0x08449060"
+ register "mrr" = "0x00007522"
+ end
+ end
device pci 7.0 on # ISA bridge
- chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
+ chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
+ device pnp 3f0.0 off end # Floppy (No connector)
+ device pnp 3f0.3 off end # Parallel port (No connector)
device pnp 3f0.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 3f0.7 on # PS/2 keyboard / mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
+ device pnp 3f0.6 on # RTC
+ irq 0x63 = 0x72
end
- device pnp 3f0.9 on # Game port
- io 0x60 = 0x201
+ device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector)
end
- device pnp 3f0.a on # Power-management events (PME)
- io 0x60 = 0x600
+ device pnp 3f0.8 on # AUX I/O
+ irq 0x24 = 0x84 # OSC
+
+ irq 0xB2 = 0x0C # Soft power status 1
+ irq 0xB3 = 0x05 # Soft power status 2
+ irq 0xC0 = 0x03 # IRQ MUX control
+
+ irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable
+ irq 0xCA = 0x09 # GP52 = IRQ8 (output)
+ irq 0xCB = 0x01 # GP53 = nROMCS (output)
+ irq 0xCC = 0x11 # GP54 = (I/O) input
+ irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
+
+ irq 0xD0 = 0x08 # GP60 = IRQ1
+ irq 0xD1 = 0x08 # GP61 = IRQ3
+ irq 0xD2 = 0x08 # GP62 = IRQ4
+ irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board
+ irq 0xD4 = 0x11 # GP64 = (I/O) input
+ irq 0xD5 = 0x11 # GP65 = (I/O) input
+ irq 0xD6 = 0x08 # GP66 = IRQ8
+ irq 0xD7 = 0x11 # GP67 = (I/O) input
+ irq 0xFA = 0x00 # read/write GP6x lines (0x88)
+
+ irq 0xE0 = 0x00 # GP10 (I/O) = output
+ irq 0xE1 = 0x01 # GP11 (I/O) = input
+ irq 0xE2 = 0x08 # GP12 = P17
+ irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low
+ irq 0xE4 = 0x00 # GP14 (I/O) = output
+ irq 0xE5 = 0x00 # GP15 (I/O) = output
+ irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open
+ irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low
+ irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
+
+ irq 0xEF = 0x00 # GP_INT2 disable
+ irq 0xF0 = 0x00 # GP_INT1 disable
+ irq 0xF1 = 0x00 # WDT_UNITS
+ irq 0xF2 = 0x00 # WDT_VAL
+ irq 0xF3 = 0x00 # WDT_CFG
+ irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt)
end
- device pnp 3f0.b on # MIDI port (MPU-401)
- io 0x60 = 0x330
- irq 0x70 = 5
+ device pnp 3f0.a off # ACPI (No support yet)
+ # irq 0x60 = 0x0C
+ # irq 0x61 = 0x80
end
end
end
device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
+ device pci 7.2 off end # USB (No connector)
+ device pci 7.3 off end # ACPI (No support yet)
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
+ # Disable UDMA/33 for lower speed if your IDE device(s) don't support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
end
- device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0f.0 on end # CardBus bridge (TI PCI1225)
- device pci 0f.1 on end # CardBus bridge (TI PCI1225)
- end
- device pci_domain 1 on # PCI domain 1
- device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
- end
- device pci_domain 2 on # PCI domain 2
- device pci 04.0 on end # NIC (DECchip 21142/43)
- device pci 04.0 on end # NIC (DECchip 21142/43)
end
end
-
projects / coreboot.git / blobdiff