Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / newisys / khepri / romstage.c

diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index e8c040950f996ae804873902c7be1da79c48b1d0..984aa9da5430f496bd319369e64394c25627c46b 100644 (file)
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -1,10 +1,9 @@
 /*
  * This code is derived from the Tyan s2882 romstage.c
  * Adapted by Stefan Reinauer <stepan@coresystems.de>
- * Additional (C) 2007 coresystems GmbH 
+ * Additional (C) 2007 coresystems GmbH
  */
 
- 
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -12,11 +11,10 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -74,18 +72,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 
  /* newisys khepri does not want the default */
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
 #include "cpu/amd/dualcore/dualcore.c"
 
 
@@ -100,11 +94,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
-                       (0xa<<3)|0, (0xa<<3)|2, 0, 0,
-                       (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+                       DIMM0, DIMM2, 0, 0,
+                       DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-                       (0xa<<3)|4, (0xa<<3)|6, 0, 0,
-                       (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+                       DIMM4, DIMM6, 0, 0,
+                       DIMM5, DIMM7, 0, 0,
 #endif
        };
 
@@ -129,13 +123,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 
 //     post_code(0x32);
-       
+
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-       
+
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);