Change all occurences of NSC to nsc in the code. The next commit

[coreboot.git] / src / mainboard / newisys / khepri / auto.c

diff --git a/src/mainboard/newisys/khepri/auto.c b/src/mainboard/newisys/khepri/auto.c
index 8b7a85d6de5bf82893f6f6fe71231ca94c030853..c0289edaa4fe3f81a0bf954bbf61fe06d00bf68e 100644 (file)
--- a/src/mainboard/newisys/khepri/auto.c
+++ b/src/mainboard/newisys/khepri/auto.c
@@ -1,28 +1,27 @@
 #define ASSEMBLY 1
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
-#include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include <cpu/amd/model_fxx_rev.h>
+#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
@@ -66,50 +65,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
        }
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-       /* Routing Table Node i 
-        *
-        * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-        *  i:    0,    1,    2,    3,    4,    5,    6,    7
-        *
-        * [ 0: 3] Request Route
-        *     [0] Route to this node
-        *     [1] Route to Link 0
-        *     [2] Route to Link 1
-        *     [3] Route to Link 2
-        * [11: 8] Response Route
-        *     [0] Route to this node
-        *     [1] Route to Link 0
-        *     [2] Route to Link 1
-        *     [3] Route to Link 2
-        * [19:16] Broadcast route
-        *     [0] Route to this node
-        *     [1] Route to Link 0
-        *     [2] Route to Link 1
-        *     [3] Route to Link 2
-        */
-
-       uint32_t ret=0x00010101; /* default row entry */
-
-       static const unsigned int rows_2p[2][2] = {
-               { 0x00090101, 0x00010808 },
-               { 0x00010404, 0x00050101 }
-       };
-
-       if(maxnodes > 2) {
-               print_debug("this mainboard is only designed for 2 cpus\r\n");
-               maxnodes=2;
-       }
-
-
-       if (!(node >= maxnodes || row >= maxnodes)) {
-               ret=rows_2p[node][row];
-       }
-
-       return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
        /* nothing to do */
@@ -122,57 +77,57 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit.c"
 
-#define CONNECTION_0_1 DOWN
-
 #include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
 #include "sdram/generic_sdram.c"
 
-#include "resourcemap.c" /* newisys khepri does not want the default */
+/* newisys khepri does not want the default */
+#include "resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define NODE_RAM(x)                     \
+       .node_id = 0+x,                 \
+       .f0 = PCI_DEV(0, 0x18+x, 0),    \
+       .f1 = PCI_DEV(0, 0x18+x, 1),    \
+       .f2 = PCI_DEV(0, 0x18+x, 2),    \
+       .f3 = PCI_DEV(0, 0x18+x, 3)
 
-static void main(void)
+static void main(unsigned long bist)
 {
-       /*
-        * GPIO28 of 8111 will control H0_MEMRESET_L
-        * GPIO29 of 8111 will control H1_MEMRESET_L
-        */
        static const struct mem_controller cpu[] = {
                {
-                       .node_id = 0,
-                       .f0 = PCI_DEV(0, 0x18, 0),
-                       .f1 = PCI_DEV(0, 0x18, 1),
-                       .f2 = PCI_DEV(0, 0x18, 2),
-                       .f3 = PCI_DEV(0, 0x18, 3),
+                       NODE_RAM(0),
                        .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
                        .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
                },
                {
-                       .node_id = 1,
-                       .f0 = PCI_DEV(0, 0x19, 0),
-                       .f1 = PCI_DEV(0, 0x19, 1),
-                       .f2 = PCI_DEV(0, 0x19, 2),
-                       .f3 = PCI_DEV(0, 0x19, 3),
+                       NODE_RAM(1),
                        .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
                        .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
                },
        };
+
        int needs_reset;
-       enable_lapic();
-       init_timer();
-       if (cpu_init_detected()) {
-               asm("jmp __cpu_reset");
-       }
-       distinguish_cpu_resets();
-       if (!boot_cpu()) {
-               stop_this_cpu();
+        unsigned nodeid;
+
+       if (bist == 0) {
+               k8_init_and_stop_secondaries();
        }
+       /* Setup the console */
        pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
        uart_init();
        console_init();
+
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        setup_khepri_resource_map();
        needs_reset = setup_coherent_ht_domain();
-       needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+       needs_reset=ht_setup_chains_x();
+
        if (needs_reset) {
-               print_info("ht reset -");
+               print_info("ht reset -\r\n");
                soft_reset();
        }
 #if 0