* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
-#define RAMINIT_SYSINFO 1
-
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
-
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-
-static void post_code(u8 value) {
- outb(value, 0x80);
-}
-
-#include "arch/i386/lib/console.c"
-#if CONFIG_USBDEBUG_DIRECT
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-#include "lib/ramtest.c"
-
+#include <console/console.h>
+#include <usbdebug.h>
+#include <lib.h>
+#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
-
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
-#define MCP55_PCI_E_X_0 1
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-#include "cpu/amd/car/copy_and_run.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
-#include "cpu/amd/model_10xxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{
- unsigned value;
- uint32_t dword;
- uint8_t byte;
+ u32 dword;
+ u8 byte;
byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
-#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
+static const u8 spd_addr[] = {
+ //first node
+ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
- mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
- early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+ early_usbdebug_init();
#endif
val = cpuid_eax(1);
post_code(0x38);
-#if FAM10_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
wants_reset = mcp55_early_setup_x();
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
- post_code(0x3E);
- memreset_setup();
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
projects / coreboot.git / blobdiff