Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / msi / ms9652_fam10 / Kconfig
index 212cd7037a63579065e4277fe6736a8b812f714f..88723b8c7f5b8bf1cd2ba4455f223627a29ee9e9 100644 (file)
@@ -4,20 +4,26 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F_1207
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDFAM10
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
+       select MCP55_USE_AZA
        select SUPERIO_WINBOND_W83627EHG
        select HAVE_BUS_CONFIG
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_DCACHE_RAM
+       select HAVE_ACPI_TABLES
        select HAVE_OPTION_TABLE
        select HAVE_HARD_RESET
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
        select AMDMCT
        select TINY_BOOTBLOCK
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
@@ -121,10 +127,6 @@ config CONSOLE_SERIAL8250
        bool
        default y
 
-config CONSOLE_VGA
-       bool
-       default y
-
 config PCI_ROM_RUN
        bool
        default y
@@ -133,14 +135,6 @@ config USBDEBUG
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x20
@@ -193,4 +187,8 @@ config HT3_SUPPORT
        bool
        default y
 
+config MCP55_PCI_E_X_0
+       int
+       default 1
+
 endif # BOARD_MSI_MS9652_FAM10