* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
return smbus_read_byte(device, address);
}
-//#define K8_4RANK_DIMM_SUPPORT 1
-
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
//set GPIO to input mode
#define MCP55_MB_SETUP \
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
+// Disabled until it's actually used:
+// #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#endif
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
- needs_reset = optimize_link_coherent_ht();
-
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
- needs_reset |= mcp55_early_setup_x();
+ needs_reset = optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ needs_reset |= mcp55_early_setup_x();
- if (needs_reset) {
- print_info("ht reset -\n");
- soft_reset();
- }
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset();
+ }
//It's the time to set ctrl now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
-
}