Drop unused and incorrect RTC_DEV for Winbond W83627EHG.

[coreboot.git] / src / mainboard / msi / ms9282 / romstage.c

diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 83f894a96550a8531d8a233cea81f2913cab0d68..6ec9daab18ccdc0bda09d4a2c56e1e00528ffddb 100644 (file)
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -22,19 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -42,10 +29,8 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
@@ -64,13 +49,9 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
 
 #include <device/pci_ids.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -100,19 +81,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-//#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 
  /* msi does not want the default */
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
@@ -123,12 +101,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
+// Disabled until it's actually used:
+// #include "cpu/amd/model_fxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -154,12 +131,12 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       // Node 0
-                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
-                       // node 1
-                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+               // Node 0
+               RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
+               RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+               // node 1
+               RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
+               RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
        };
 
        unsigned bsp_apicid = 0;
@@ -184,18 +161,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
-       w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        uart_init();
-        console_init();
+       w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       uart_init();
+       console_init();
 
-       /* Halt if there was a built in self test failure */
-       report_bist_failure(bist);
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
 
-        setup_ms9282_resource_map();
+       setup_ms9282_resource_map();
 
-       setup_coherent_ht_domain();
+       setup_coherent_ht_domain();
 
-        wait_all_core0_started();
+       wait_all_core0_started();
 
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
@@ -204,16 +181,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-       needs_reset = optimize_link_coherent_ht();
+       init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
-       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+       needs_reset = optimize_link_coherent_ht();
+       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+       needs_reset |= mcp55_early_setup_x();
 
-        needs_reset |= mcp55_early_setup_x();
-
-               if (needs_reset) {
-                       print_info("ht reset -\n");
-                       soft_reset();
-               }
+        if (needs_reset) {
+               print_info("ht reset -\n");
+                soft_reset();
+        }
 
         //It's the time to set ctrl now;
         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
@@ -228,11 +205,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 #endif
 
-       memreset_setup();
-
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
        post_cache_as_ram();
-
 }