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Simplify a few code chunks, fix whitespace and indentation.
[coreboot.git] / src / mainboard / msi / ms9185 / romstage.c
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 519713ff023cb19b0947a55b6cfc8e8143d7f735..ffe728d3e5756e1a45403d09d1edc002df5d5deb 100644 (file)
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -23,18 +23,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_NB_CFG_54 1
-
-//used by raminit
-
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -45,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
@@ -53,23 +40,19 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <reset.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -100,38 +83,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
- /* msi does not want the default */
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define RC0 (0x10<<8)
-#define RC1 (0x01<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
+#include <spd.h>
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
+#define RC0 (0x10<<8)
+#define RC1 (0x01<<8)
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       //first node
-                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
-                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
+                      //first node
+                       RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+                       RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
                        //second node
                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
@@ -146,24 +114,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
                bcm5785_enable_rom();
-
                bcm5785_enable_lpc();
-
                //enable RTC
                pc87417_enable_dev(RTC_DEV);
         }
 
-        if (bist == 0) {
+        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-        }
-
-//     post_code(0x32);
 
-       pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+        pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -172,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-       printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+       printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
        setup_ms9185_resource_map();
 #if 0
-        dump_pci_device(PCI_DEV(0, 0x18, 0));
+       dump_pci_device(PCI_DEV(0, 0x18, 0));
        dump_pci_device(PCI_DEV(0, 0x19, 0));
 #endif
 
@@ -196,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        /* it will set up chains and store link pair for optimization later */
-        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+       ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
        bcm5785_early_setup();
 
@@ -206,27 +167,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if SET_FIDVID == 1
-
+#if CONFIG_SET_FIDVID
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
         }
-
-       enable_fid_change();
-
-       enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
+        enable_fid_change();
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
         init_fidvid_bsp(bsp_apicid);
-
         // show final fid and vid
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
         }
 #endif
 
@@ -280,6 +234,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        post_cache_as_ram();
-
 }
-
my coreboot WIP stuff (asus m5a99x-evo board)