* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
-// #define DEBUG_SMBUS 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1
#endif
/* Used by init_cpus and fidvid. */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void) {}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
+
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
}
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- unsigned int last_boot_normal_x = last_boot_normal();
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_x)
- goto normal_image;
- else
- goto fallback_image;
- }
-
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
-
- sio_setup();
-
- /* Setup the MCP55. */
- mcp55_enable_rom();
-
- /* Is this a deliberate reset by the BIOS? */
- if (bios_reset_detected() && last_boot_normal_x) {
- goto normal_image;
- }
- /* This is the primary CPU. How should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
-
-normal_image:
- __asm__ volatile ("jmp __normal_image":
- :"a" (bist), "b"(cpu_init_detectedx)
- );
-
-fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- __asm__ volatile ("jmp __fallback_image":
- :"a" (bist), "b"(cpu_init_detectedx)
- )
-#endif
- ;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-#if CONFIG_USE_FAILOVER_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
-#else
- real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
-#endif
- real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
- struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
int needs_reset = 0;
unsigned bsp_apicid = 0;
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0. */
+ /* Allow the HT devices to be found. */
+ enumerate_ht_chain();
+
+ sio_setup();
+
+ /* Setup the MCP55. */
+ mcp55_enable_rom();
+ }
+
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
#endif
console_init();
- print_debug("*sysinfo range: [");
- print_debug_hex32(sysinfo);
- print_debug(",");
- print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
- print_debug(")\r\n");
-
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
- print_debug("\r\n");
+ print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
enable_fid_change();
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
enable_smbus();
- memreset_setup();
-
- /* Do we need apci timer, tsc...., only debug need it for better output */
/* All AP stopped? */
- // init_timer(); /* Need to use TMICT to synconize FID/VID. */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
-#endif
projects / coreboot.git / blobdiff