Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / msi / ms7260 / romstage.c

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 799c05e3c6cb53c17848b4663abf10c820051e18..a5fbffbe4b883a1238929d58dafabb6f0bc597a3 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -75,7 +75,7 @@
 
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 /* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
@@ -83,7 +83,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void) {}
 static void memreset(int controllers, const struct mem_controller *ctrl) {}
 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
 
@@ -93,10 +92,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
+
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -115,7 +115,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -144,16 +144,17 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
+               // Node 0
                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
                (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+               // Node 1
                (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
                (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
        };
 
-       struct sys_info *sysinfo =
-           (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+               + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
 
@@ -236,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        }
 #endif
 
+       init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
        needs_reset |= optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        needs_reset |= mcp55_early_setup_x();
@@ -252,11 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        enable_smbus();
 
-       memreset_setup();
-
-       /* Do we need apci timer, tsc...., only debug need it for better output */
        /* All AP stopped? */
-       // init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);