#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void) {}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
+
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
- struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
int needs_reset = 0;
unsigned bsp_apicid = 0;
enable_smbus();
- memreset_setup();
-
/* Do we need apci timer, tsc...., only debug need it for better output */
/* All AP stopped? */
// init_timer(); /* Need to use TMICT to synconize FID/VID. */