__PRE_RAM__ is now correctly specified in the Makefile. No need to hack it into

[coreboot.git] / src / mainboard / msi / ms7260 / romstage.c

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 7a8bf13a79e9db56716d34a00f4065e7bbf161cc..725f0f6bd33053a21de63e8c7fb2b79d4956f871 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -21,10 +21,9 @@
  */
 
 #define ASSEMBLY 1
-#define __PRE_RAM__
+
 
 // #define CACHE_AS_RAM_ADDRESS_DEBUG 1
-// #define DEBUG_SMBUS 1
 // #define RAM_TIMING_DEBUG 1
 // #define DQS_TRAIN_DEBUG 1
 // #define RES_DEBUG 1
@@ -59,8 +58,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -74,15 +71,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -130,10 +123,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -155,74 +144,7 @@ static void sio_setup(void)
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-       unsigned int last_boot_normal_x = last_boot_normal();
-
-       /* Is this a CPU only reset? Or is this a secondary CPU? */
-       if ((cpu_init_detectedx) || (!boot_cpu())) {
-               if (last_boot_normal_x)
-                       goto normal_image;
-               else
-                       goto fallback_image;
-       }
-
-       /* Nothing special needs to be done to find bus 0. */
-       /* Allow the HT devices to be found. */
-       enumerate_ht_chain();
-
-       sio_setup();
-
-       /* Setup the MCP55. */
-       mcp55_enable_rom();
-
-       /* Is this a deliberate reset by the BIOS? */
-       if (bios_reset_detected() && last_boot_normal_x) {
-               goto normal_image;
-       }
-       /* This is the primary CPU. How should I boot? */
-       else if (do_normal_boot()) {
-               goto normal_image;
-       } else {
-               goto fallback_image;
-       }
-
-normal_image:
-       __asm__ volatile ("jmp __normal_image":
-                         :"a" (bist), "b"(cpu_init_detectedx)
-       );
-
-fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-       __asm__ volatile ("jmp __fallback_image":
-                         :"a" (bist), "b"(cpu_init_detectedx)
-       )
-#endif
-       ;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-#if CONFIG_USE_FAILOVER_IMAGE == 1
-       failover_process(bist, cpu_init_detectedx);
-#else
-       real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-       failover_process(bist, cpu_init_detectedx);
-#endif
-       real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
@@ -238,6 +160,17 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
 
+       if (!cpu_init_detectedx && boot_cpu()) {
+               /* Nothing special needs to be done to find bus 0. */
+               /* Allow the HT devices to be found. */
+               enumerate_ht_chain();
+
+               sio_setup();
+
+               /* Setup the MCP55. */
+               mcp55_enable_rom();
+       }
+
        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
@@ -257,12 +190,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
        console_init();
 
-       print_debug("*sysinfo range: [");
-       print_debug_hex32(sysinfo);
-       print_debug(",");
-       print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
-       print_debug(")\r\n");
-
+       printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
        print_debug("bsp_apicid=");
        print_debug_hex8(bsp_apicid);
        print_debug("\r\n");
@@ -339,4 +267,3 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();
 }
 
-#endif