Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / msi / ms7260 / romstage.c

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 167fa34e265c7226f04d58dc3a8161ae4fad261b..329c679dee89ff26e30ca03729c705af9bc8da96 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -20,30 +20,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
-// #define RAM_TIMING_DEBUG 1
-// #define DQS_TRAIN_DEBUG 1
-// #define RES_DEBUG 1
-
-#define RAMINIT_SYSINFO 1
-#define K8_ALLOCATE_IO_RANGE 1
-#define QRANK_DIMM_SUPPORT 1
-#if CONFIG_LOGICAL_CPUS == 1
-#define SET_NB_CFG_54 1
-#endif
-
-/* Used by init_cpus and fidvid. */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
-#define DBGP_DEFAULT 7
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -52,36 +32,28 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-#include "lib/ramtest.c"
+#include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
+#include <lib.h>
+#include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl) {}
 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
 
@@ -95,15 +67,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-#define MCP55_PCI_E_X_0 0
-
 #define MCP55_MB_SETUP \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
@@ -114,11 +80,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -144,11 +108,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
                // Node 0
-               (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-               (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
                // Node 1
-               (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-               (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
        };
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
@@ -181,9 +145,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_mb_resource_map();
        uart_init();
        report_bist_failure(bist); /* Halt upon BIST failure. */
-#if CONFIG_USBDEBUG_DIRECT
-       mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+       early_usbdebug_init();
 #endif
        console_init();
 
@@ -214,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Set up chains and store link pair for optimization later. */
        ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        {
                msr_t msr = rdmsr(0xc0010042);
                print_debug("begin msr fid, vid ");
@@ -261,4 +225,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* bsp switch stack to RAM and copy sysinfo RAM now. */
        post_cache_as_ram();
 }
-