Drop dead K8_SCAN_PCI_BUS code. It's a bad idea to scan the PCI busses before

[coreboot.git] / src / mainboard / msi / ms7260 / cache_as_ram_auto.c

diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
index ffbeaf43aeaa8c9e8aa2bbe0fb801c9f393c1101..ed84a426b2da3308dcf199c5c89b92db4cdf5ede 100644 (file)
--- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -31,7 +31,6 @@
 
 #define RAMINIT_SYSINFO 1
 #define K8_ALLOCATE_IO_RANGE 1
-// #define K8_SCAN_PCI_BUS 1           /* ? */
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
@@ -43,13 +42,14 @@
 /* If we want to wait for core1 done before DQS training, set it to 0. */
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
 #define DBGP_DEFAULT 7
 
 #include <stdint.h>
+#include <string.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
@@ -59,7 +59,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
@@ -67,7 +67,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
 #endif
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -81,12 +81,9 @@
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 
 #include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -109,7 +106,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -135,7 +132,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -196,7 +193,7 @@ normal_image:
        );
 
 fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
        __asm__ volatile ("jmp __fallback_image":
                          :"a" (bist), "b"(cpu_init_detectedx)
        )
@@ -209,21 +206,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT == 1
-#if USE_FAILOVER_IMAGE == 1
+#if CONFIG_HAVE_FAILOVER_BOOT == 1
+#if CONFIG_USE_FAILOVER_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);
 #else
        real_main(bist, cpu_init_detectedx);
 #endif
 #else
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);
 #endif
        real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -237,7 +234,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        };
 
        struct sys_info *sysinfo =
-           (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+           (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
 
@@ -248,7 +245,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        pnp_enter_ext_func_mode(SERIAL_DEV);
        /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
        pnp_write_config(SERIAL_DEV, 0x24, 0);
-       w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
+       w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
        pnp_exit_ext_func_mode(SERIAL_DEV);
 
        setup_mb_resource_map();
@@ -270,7 +267,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        print_debug_hex8(bsp_apicid);
        print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
        /* In BSP so could hold all AP until sysinfo is in RAM. */
        set_sysinfo_in_ram(0);
 #endif