Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / msi / ms7135 / romstage.c

diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 67eb446c9c7e852db4aaa1673fc65c538127b4fc..74e966d1484742af6b4e7b2229bbc38ca9c224d7 100644 (file)
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -22,15 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
-
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS == 1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -38,21 +29,14 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-/* Used by ck804_early_setup(). */
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
+#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -62,11 +46,9 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
-static void memreset_setup(void)
-{
-       /* FIXME: Nothing to do? */
-}
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -87,11 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -114,7 +93,7 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-               (0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
+               DIMM0, DIMM1, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
@@ -132,16 +111,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                enumerate_ht_chain();
 
                sio_setup();
-
-               /* Setup the ck804 */
-               ck804_enable_rom();
        }
 
        if (bist == 0) {
                bsp_apicid = init_cpus(cpu_init_detectedx);
        }
 
-       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 
@@ -183,7 +159,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_smbus_registers();
 #endif
 
-       memreset_setup();
        sdram_initialize(nodes, ctrl);
 
 #if 0
@@ -193,4 +168,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-