Remove various .c #includes from Intel 440BX/82371EB boards.

[coreboot.git] / src / mainboard / msi / ms6156 / romstage.c

diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index 45c97eea6acb0484ac18a3fc1cc302760113bba5..630f313b1b7290167dcb2307db14e1d04038c806 100644 (file)
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -26,10 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
        w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -53,9 +51,6 @@ void main(unsigned long bist)
        console_init();
        report_bist_failure(bist);
 
-       /* Enable access to the full ROM chip, needed very early by CBFS. */
-       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
        enable_smbus();
        dump_spd_registers();
        sdram_set_registers();