* clean up all but two warnings on artecgroup dbe61

[coreboot.git] / src / mainboard / lippert / roadrunner-lx / romstage.c

diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index efaf1dd6bedcf24fddba2c0d8382a1965ddd7a41..8aedd6380e44f6e980ce4dcabe1406f1d9374e7f 100644 (file)
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -60,39 +60,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-       msr_t msr;
-
-       /* Setup access to the cache for under 1MB. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x1000A000;    /* 0-A0000 write back */
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x0;           /* Write back */
-       msr.lo = 0x0;
-       wrmsr(CPU_RCONF_A0_BF, msr);
-       wrmsr(CPU_RCONF_C0_DF, msr);
-       wrmsr(CPU_RCONF_E0_FF, msr);
-
-       /* Setup access to the cache for under 640K. Note MC not setup yet. */
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU0 + 0x21, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {  // hi=data, lo=index
        0x0707,         // select LDN 7 (GPIO, SPI, watchdog, ...)
@@ -128,7 +96,7 @@ static void mb_gpio_init(void)
        it8712f_exit_conf();
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
        post_code(0x01);
 
@@ -150,6 +118,9 @@ void cache_as_ram_main(void)
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
        cpuRegInit();