Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / lippert / roadrunner-lx / romstage.c

diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index efaf1dd6bedcf24fddba2c0d8382a1965ddd7a41..0100caedc372bbca9f55af42821fd02dd0042999 100644 (file)
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -27,15 +27,13 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
@@ -43,8 +41,6 @@
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
@@ -60,52 +56,19 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-       msr_t msr;
-
-       /* Setup access to the cache for under 1MB. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x1000A000;    /* 0-A0000 write back */
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x0;           /* Write back */
-       msr.lo = 0x0;
-       wrmsr(CPU_RCONF_A0_BF, msr);
-       wrmsr(CPU_RCONF_C0_DF, msr);
-       wrmsr(CPU_RCONF_E0_FF, msr);
-
-       /* Setup access to the cache for under 640K. Note MC not setup yet. */
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU0 + 0x21, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {  // hi=data, lo=index
        0x0707,         // select LDN 7 (GPIO, SPI, watchdog, ...)
-       0x1E2C,         // disable ATXPowerGood - will cause a reboot!
-       0x0423,         // don't delay POWerOK1/2
-       0x9072,         // watchdog triggers POWOK, counts seconds
+       0x1E2C,         // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal
+       0x1423,         // don't delay PoWeROK1/2 - triggers 2nd reset
+       0x9072,         // watchdog triggers PWROK, counts seconds
 #if !CONFIG_USE_WATCHDOG_ON_BOOT
-       0x0073, 0x0074, // disable watchdog by setting timeout to 0
+       0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
 #endif
        0xBF25, 0x372A, 0xF326, // select GPIO function for most pins
        0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1)
-       0x1E2C,         // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled
-       0x46B8, 0x0CB9, // enable pullups
+       0x46B8, 0x0CB9, // enable pullups on RS485_EN
        0x36C0,         // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1
        0xFFC3,         // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector)
        0x26C8,         // config GP15,12,11 as output; GP14 as input
@@ -128,12 +91,12 @@ static void mb_gpio_init(void)
        it8712f_exit_conf();
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
        post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -150,9 +113,12 @@ void cache_as_ram_main(void)
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
@@ -162,4 +128,3 @@ void cache_as_ram_main(void)
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-