-#define ASSEMBLY 1
-
-
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/gx2/raminit.h"
/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
msr_t msr;
/* 1. Initialize GLMC registers base on SPD values,
* Hard coded as XpressROM for now */
- //print_debug("sdram_enable step 1\r\n");
+ //print_debug("sdram_enable step 1\n");
msr = rdmsr(0x20000018);
msr.hi = 0x10076013;
msr.lo = 0x3400;
__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
__builtin_wrmsr(0x50002001, 0x27, 0x0);
__builtin_wrmsr(0x4c002001, 0x1, 0x0);
}
-
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
outb( 0x87, 0x4E); //enter SuperIO configuration mode
outb( 0x87, 0x4E);
-
outb(0x20, 0x4e);
temp = inb(0x4f);
print_debug_hex8(temp);
// ram_check(0x00000000, 640*1024);
}
+