i82801gx: replace cafed00d/cafebabe by defines

[coreboot.git] / src / mainboard / lenovo / x60 / romstage.c

diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 9ee375aae740762e8c92651d3f2c8a00260d8273..c993a3565f192fd9eebbf3f278bef36e69318de5 100644 (file)
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -37,6 +37,7 @@
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
+#include "dock.h"
 
 void setup_ich7_gpios(void)
 {
@@ -100,97 +101,20 @@ static void ich7_enable_lpc(void)
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
 }
 
-static void pnp_write_register(device_t dev, int reg, int val)
-{
-       unsigned int port = dev >> 8;
-       outb(reg, port);
-       outb(val, port+1);
-}
-
-static void dock_write_register(int reg, int value)
-{
-       outb(reg, 0x164e);
-       outb(value, 0x164f);
-       /* original software reads the chip id after every
-          I/O operation. Not sure if they are doing it for
-          some code switching depending on hardware or just
-          to have a delay after every operation.
-
-          Do it the same way for now, we may remove it later
-          if it isn't needed
-       */
-       outb(0x20, 0x164e);
-       inb(0x164f);
-}
-
-static void dock_dlpc_init(void)
-{
-       /* Select DLPC module */
-       dock_write_register(0x07, 0x19);
-       /* DLPC Base Address 0x164c */
-       dock_write_register(0x60, 0x16);
-       dock_write_register(0x61, 0x4c);
-       /* Activate DLPC */
-       dock_write_register(0x30, 0x01);
-       outb(0x07, 0x164c);
-
-       while(!(inb(0x164c) & 8))
-               udelay(100 * 100);
-}
-
-static void dock_gpio_set_mode(int port, int mode)
-{
-       dock_write_register(0xf0, port);
-       dock_write_register(0xf1, mode);
-
-}
-
-static void dock_gpio_init(void)
-{
-       /* Select GPIO module */
-       dock_write_register(0x07, 0x07);
-       /* GPIO Base Address 0x1680 */
-       dock_write_register(0x60, 0x16);
-       dock_write_register(0x61, 0x80);
-
-       /* Activate GPIO */
-       dock_write_register(0x30, 0x01);
-
-       dock_gpio_set_mode(0x00, 3);
-       dock_gpio_set_mode(0x01, 3);
-       dock_gpio_set_mode(0x02, 0);
-       dock_gpio_set_mode(0x03, 3);
-       dock_gpio_set_mode(0x04, 4);
-       dock_gpio_set_mode(0x20, 4);
-       dock_gpio_set_mode(0x21, 4);
-       dock_gpio_set_mode(0x23, 4);
-}
-
-static void connect_dock(void)
-{
-       /* Enable 14.318MHz CLK on CLKIN */
-       dock_write_register(0x29, 0x00);
-       dock_write_register(0x29, 0xa0);
-       dock_gpio_init();
-       /* Assert D_PLTRST# */
-       outb(0xfe, 0x1680);
-       dock_dlpc_init();
-       /* Deassert D_PLTRST# */
-       outb(0xff, 0x1680);
-}
-
 static void early_superio_config(void)
 {
-       device_t dev;
+       int timeout = 100000;
+       device_t dev = PNP_DEV(0x2e, 3);
+
+       pnp_write_config(dev, 0x29, 0x06);
 
-       dev=PNP_DEV(0x2e, 0x00);
-       pnp_write_register(dev, 0x29, 0x06);
+       while(!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
+               udelay(1000);
 
        /* Enable COM1 */
-       pnp_write_register(dev, 0x07, 0x03);
-       pnp_write_register(dev, 0x60, 0x03);
-       pnp_write_register(dev, 0x61, 0xf8);
-       pnp_write_register(dev, 0x30, 0x01);
+       pnp_set_logical_device(dev);
+       pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
+       pnp_set_enable(dev, 1);
 }
 
 static void rcba_config(void)
@@ -224,6 +148,14 @@ static void rcba_config(void)
        /* Disable unused devices */
        RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
        RCBA32(0x3418) |= (1 << 0); // Required.
+
+       /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
+       RCBA32(0x1e84) = 0x00020001;
+       RCBA32(0x1e80) = 0x0000fe01;
+
+       /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+       RCBA32(0x1e9c) = 0x000200f0;
+       RCBA32(0x1e98) = 0x000c0801;
 }
 
 static void early_ich7_init(void)
@@ -286,6 +218,7 @@ void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
+       const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
 
        if (bist == 0)
                enable_lapic();
@@ -297,17 +230,16 @@ void main(unsigned long bist)
 
        ich7_enable_lpc();
 
-       connect_dock();
-
-       early_superio_config();
-
-       /* Set up the console */
-       uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
+       /* dock_init initializes the DLPC switch on
+        *  thinpad side, so this is required even
+        *  if we're undocked.
+        */
+       if (!dlpc_init() && dock_present()) {
+               dock_connect();
+               early_superio_config();
+               /* Set up the console */
+       }
 
        console_init();
 
@@ -349,7 +281,7 @@ void main(unsigned long bist)
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, spd_addrmap);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
@@ -403,7 +335,7 @@ void main(unsigned long bist)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
-               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
        }
 #endif
        /* Set legacy Brightness control to full brightness */