/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
*/
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#define __PRE_RAM__
-
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-/* Usually system firmware turns off system memory clock signals to
- * unused SO-DIMM slots to reduce EMI and power consumption.
- * However, the Kontron 986LCD-M does not like unused clock signals to
- * be disabled. If other similar mainboard occur, it would make sense
- * to make this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function. For now a
- * #define will do.
- */
-#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
+#include <lib.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-
+#include <usbdebug.h>
#include "superio/winbond/w83627thg/w83627thg.h"
-
+#include <pc80/mc146818rtc.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
#include <console/console.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
#include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+#include "superio/winbond/w83627thg/early_serial.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
{
- printk_debug(" GPIOS...");
+ printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
}
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/reset_test.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
static void ich7_enable_lpc(void)
{
+ int lpt_en = 0;
+ if (read_option(lpt, 0) != 0) {
+ lpt_en = 1<<2; // enable LPT
+ }
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1/COM2/KBD/SuperIO1+2
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
// Enable HWM at 0xa00
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
// COM3 decode
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
// COM4 decode
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
- // io 0x300 decode
+ // io 0x300 decode
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
}
-
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
static void early_superio_config_w83627thg(void)
{
device_t dev;
-
+
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_ext_func_mode(dev);
pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627THG_SP2);
+ dev=PNP_DEV(0x4e, W83627THG_SP2);
pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
* would essentially disable all three ethernet ports of the mainboard.
* It's possible to rename the ports to achieve compatibility to the
* PCI spec but this will confuse all (static!) tables containing
- * interrupt routing information.
+ * interrupt routing information.
* To avoid this, we enable (unused) port 6 and swap it with port 1
* in the case that ethernet port 1 is disabled. Since no devices
* are connected to that port, we don't have to worry about interrupt
reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
- if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
- printk_debug("Disabling ethernet adapter 1.\n");
+ if (read_option(ethernet1, 0) != 0) {
+ printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
reg32 |= FD_PCIE1;
}
- if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
- printk_debug("Disabling ethernet adapter 2.\n");
+ if (read_option(ethernet2, 0) != 0) {
+ printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
reg32 |= FD_PCIE2;
} else {
if (reg32 & FD_PCIE1)
port_shuffle = 1;
}
- if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
- printk_debug("Disabling ethernet adapter 3.\n");
+ if (read_option(ethernet3, 0) != 0) {
+ printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
reg32 |= FD_PCIE3;
} else {
if (reg32 & FD_PCIE1)
RCBA32(0x2034) = reg32;
}
-#include "southbridge/intel/i82801gx/cmos_failover.c"
-
#include <cbmem.h>
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM__ being set during CAR stage (in order to compile the
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
+
+ /* Force PCIRST# */
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ udelay(200 * 1000);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
early_superio_config_w83627thg();
/* Set up the console */
- uart_init();
-
-#if CONFIG_USBDEBUG_DIRECT
- i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
- early_usbdebug_direct_init();
-#endif
-
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
- printk_debug("soft reset detected.\n");
- boot_mode = 1;
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ outb(0x6, 0xcf9);
+ while (1) asm("hlt");
}
/* Perform some early chipset initialization required
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk_debug("PM1_CNT: %08x\n", reg32);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
- printk_debug("Resume from S3 detected.\n");
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else
- printk_debug("Resume from S3 detected, but disabled.\n");
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif
}
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-
+
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
*/
rcba_config();
/* This will not work if TSEG is in place! */
u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
- printk_debug("TOM: 0x%08x\n", tom);
+ printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000);
//ram_check(0x00100000, tom);
}
#endif
#endif
+ quick_ram_check();
+
MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME
* memory completely, but that's a wonderful clean up task for another
* day.
*/
- if (resume_backup_memory)
+ if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
}
#endif
}
-
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