Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / kontron / 986lcd-m / romstage.c

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index cb400347516f6750df537ccd3af28cde93b54f7d..20d80ee648a206529dc542120b1819bb5f74d790 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -19,52 +19,29 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-/* Usually system firmware turns off system memory clock signals to
- * unused SO-DIMM slots to reduce EMI and power consumption.
- * However, the Kontron 986LCD-M does not like unused clock signals to
- * be disabled. If other similar mainboard occur, it would make sense
- * to make this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function. For now a
- * #define will do.
- */
-#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
+#include <lib.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
+#include <usbdebug.h>
 #include "superio/winbond/w83627thg/w83627thg.h"
-
+#include <pc80/mc146818rtc.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include <usbdebug_direct.h>
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -80,18 +57,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ
@@ -367,22 +332,20 @@ void main(unsigned long bist)
                enable_lapic();
        }
 
-       ich7_enable_lpc();
-
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-       udelay(200);
+       udelay(200 * 1000);
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-       udelay(200);
 
+       ich7_enable_lpc();
        early_superio_config_w83627thg();
 
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       i82801gx_enable_usbdebug(1);
+       early_usbdebug_init();
 #endif
 
        console_init();
@@ -485,4 +448,3 @@ void main(unsigned long bist)
        }
 #endif
 }
-