Update Kontron board
[coreboot.git] / src / mainboard / kontron / 986lcd-m / Config.lb
index 5be778c0f04d99f3820d1ad4e75c1d5e6d0d8936..833478bb79e8307878b85fdd87bf87fde168f6fa 100644 (file)
@@ -82,7 +82,7 @@ if HAVE_ACPI_TABLES
        object acpi_tables.o
        makerule dsdt.c
                depends "$(MAINBOARD)/dsdt.dsl"
-               action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
+               action  "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
                action  "mv $(PWD)/dsdt.hex dsdt.c"
        end
        object ./dsdt.o
@@ -101,7 +101,7 @@ else
 
 makerule ./auto.inc
        depends "$(MAINBOARD)/auto.c option_table.h"
-       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I.  $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -g -dA -fverbose-asm -Wall -c -S -o $@"
+       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I.  $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@"
        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -180,14 +180,25 @@ chip northbridge/intel/i945
                device pci 01.0 off end # i945 PCIe root port
                chip drivers/pci/onboard
                        device pci 02.0 on end # vga controller
-                       register "rom_address" = "0xfff00000"
+                       # register "rom_address" = "0xfffc0000" # 256 KB image
+                       # register "rom_address" = "0xfff80000" # 512 KB image
+                       register "rom_address" = "0xfff00000" # 1 MB image
                end
                device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx
+                       register "pirqa_routing" = "0x05"
+                       register "pirqb_routing" = "0x07"
+                       register "pirqc_routing" = "0x06"
+                       register "pirqd_routing" = "0x07"
+                       register "pirqe_routing" = "0x80"
+                       register "pirqf_routing" = "0x80"
+                       register "pirqg_routing" = "0x80"
+                       register "pirqh_routing" = "0x05"
+
                         register "ide_legacy_combined" = "0x1"
                         register "ide_enable_primary" = "0x1"
-                        register "ide_enable_secondary" = "0x1"
+                        register "ide_enable_secondary" = "0x0"
                         register "sata_ahci" = "0x0"
 
                        device pci 1b.0 on end # High Definition Audio