Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.

[coreboot.git] / src / mainboard / jetway / pa78vm5 / romstage.c

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 122c12a23c220a448d2c67abddb7476f9a289450..24302fe19a195fb7e2ee530710eaa477254c04e1 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -67,6 +67,11 @@ static int smbus_read_byte(u32 device, u32 address);
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
 #endif
 
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -146,6 +151,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
+
+#if CONFIG_USBDEBUG
+       sb700_enable_usbdebug(0);
+       early_usbdebug_init();
+#endif
+
        console_init();
        printk(BIOS_DEBUG, "\n");