Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / jetway / j7f24 / romstage.c

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 1fa2f0857b72809b29f896c942cc9fc817d577e1..daacd1bebd62fbe8474264df647d947443ee062e 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -34,6 +34,7 @@
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 #include <lib.h>
+#include <spd.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
@@ -52,7 +53,8 @@ static void enable_mainboard_devices(void)
 {
        device_t dev;
 
-       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+                               PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
        if (dev == PCI_DEV_INVALID)
                die("Southbridge not found!!!\n");
 
@@ -81,7 +83,7 @@ static const struct mem_controller ctrl = {
        .d0f4 = 0x4000,
        .d0f7 = 0x7000,
        .d1f0 = 0x8000,
-       .channel0 = { 0x50 },
+       .channel0 = { DIMM0 },
 };
 
 void main(unsigned long bist)
@@ -93,21 +95,15 @@ void main(unsigned long bist)
        uart_init();
        console_init();
 
-       print_spew("In romstage.c:main()\n");
-
        enable_smbus();
        smbus_fixup(&ctrl);
 
        /* Halt if there was a built-in self test failure. */
        report_bist_failure(bist);
 
-       print_debug("Enabling mainboard devices\n");
        enable_mainboard_devices();
 
        ddr_ram_setup(&ctrl);
 
        /* ram_check(0, 640 * 1024); */
-
-       print_spew("Leaving romstage.c:main()\n");
 }
-