amd/amd8111: Move HAVE_HARD_RESET to southbridge

[coreboot.git] / src / mainboard / iwill / dk8x / Kconfig

diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig
index 961a25a9c56b6d8c2c34e84a77ebdc81e58e9810..9216078bc856806f126e5ea68a580995017cc3a9 100644 (file)
--- a/src/mainboard/iwill/dk8x/Kconfig
+++ b/src/mainboard/iwill/dk8x/Kconfig
@@ -1,109 +1,61 @@
-config BOARD_IWILL_DK8X
-       bool "DK8X"
+if BOARD_IWILL_DK8X
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
-       select CPU_AMD_K8
        select CPU_AMD_SOCKET_940
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_AMD_AMD8111
        select SOUTHBRIDGE_AMD_AMD8131
-       select SUPERIO_WINBOND_W83627THF
+       select SUPERIO_WINBOND_W83627THG
+       select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_PRINTK_IN_CAR
-       select USE_DCACHE_RAM
-       select HAVE_HARD_RESET
-       select IOAPIC
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select WAIT_BEFORE_CPUS_INIT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
        default iwill/dk8x
-       depends on BOARD_IWILL_DK8X
-
-config DCACHE_RAM_BASE
-       hex
-       default 0xc8000
-       depends on BOARD_IWILL_DK8X
-
-config DCACHE_RAM_SIZE
-       hex
-       default 0x08000
-       depends on BOARD_IWILL_DK8X
-
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-       hex
-       default 0x01000
-       depends on BOARD_IWILL_DK8X
 
 config APIC_ID_OFFSET
        hex
-       default 0x8
-       depends on BOARD_IWILL_DK8X
-
-config LB_CKS_RANGE_END
-       int
-       default 122
-       depends on BOARD_IWILL_DK8X
-
-config LB_CKS_LOC
-       int
-       default 123
-       depends on BOARD_IWILL_DK8X
+       default 0x0
 
 config MAINBOARD_PART_NUMBER
        string
        default "DK8X"
-       depends on BOARD_IWILL_DK8X
-
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-       depends on BOARD_IWILL_DK8X
 
 config MAX_CPUS
        int
-       default 4
-       depends on BOARD_IWILL_DK8X
+       default 2
 
 config MAX_PHYSICAL_CPUS
        int
        default 2
-       depends on BOARD_IWILL_DK8X
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-       depends on BOARD_IWILL_DK8X
 
 config SB_HT_CHAIN_ON_BUS0
        int
-       default 2
-       depends on BOARD_IWILL_DK8X
+       default 0
 
 config HT_CHAIN_END_UNITID_BASE
        hex
-       default 0x6
-       depends on BOARD_IWILL_DK8X
+       default 0x20
 
 config HT_CHAIN_UNITID_BASE
        hex
-       default 0xa
-       depends on BOARD_IWILL_DK8X
-
-config USE_INIT
-       bool
-       default n
-       depends on BOARD_IWILL_DK8X
+       default 0x1
 
 config SERIAL_CPU_INIT
        bool
        default n
-       depends on BOARD_IWILL_DK8X
 
 config IRQ_SLOT_COUNT
        int
-       default 11
-       depends on BOARD_IWILL_DK8X
+       default 9
+
+endif # BOARD_IWILL_DK8X